參數(shù)資料
型號(hào)： S29GL01GP90TFIR12
廠商： Spansion Inc.
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述： 3.0伏只頁(yè)面模式閃存具有90納米MirrorBit工藝技術(shù)
文件頁(yè)數(shù)： 20/77頁(yè)
文件大小： 2121K
代理商： S29GL01GP90TFIR12
20
S29GL-P MirrorBit
Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
7.2
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.3
VersatileIO
TM
(V
IO
) Control
The VersatileIO
TM
(V
IO
) control allows the host system to set the voltage levels that the device generates and
tolerates on all inputs and outputs (address, control, and DQ signals). V
IO
range is 1.65 to V
CC
. See
Ordering
Information
on page 9
for V
IO
options on this device.
For example, a V
IO
of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data bus.
7.4
Read
All memories require access time to output array data. In a read operation, data is read from one memory
location at a time. Addresses are presented to the device in random order, and the propagation delay through
the device causes the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from the
memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to V
IL
.
WE# must remain at V
IH
. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-
DQ0 after address access time (t
ACC
), which is equal to the delay from stable addresses to valid output data.
The OE# signal must be driven to V
IL
. Data is output on DQ15-DQ0 pins after the access time (t
OE
) has
elapsed from the falling edge of OE#, assuming the t
ACC
access time has been meet.
7.5
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3.
Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within a page. The
microprocessor supplies the specific word location.
The random or initial page access is equal to t
ACC
or t
CE
and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to t
PACC
. When CE# is de-
asserted and reasserted for a subsequent access, the access time is t
ACC
or t
CE
. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
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