參數(shù)資料
型號: S29AL016D90MFI013
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 16 MEGABIT CMOS 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY
中文描述: 1M X 16 FLASH 3V PROM, 90 ns, PDSO44
封裝: 28.20 X 13.30 MM, LEAD FREE, MO-180AAA, SOP-44
文件頁數(shù): 10/58頁
文件大?。?/td> 1037K
代理商: S29AL016D90MFI013
10
S29AL016D
S29AL016D_00_A2 December 17, 2004
P r e l i m i n a r y
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
Table 1
lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. S29AL016D Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH
), A19:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in
the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Operation
CE#
L
L
V
CC
±
0.3 V
L
X
OE# W E#
L
H
RESET#
H
H
V
CC
±
0.3 V
H
L
Addresses
(
Note 1
)
A
IN
A
IN
DQ0–
DQ7
D
OUT
D
IN
DQ8– DQ15
BYTE#
= V
IH
D
OUT
D
IN
BYTE#
= V
IL
Read
Write
H
L
DQ8–DQ14 = High-Z,
DQ15 = A-1
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
H
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Protect (
Note 2
)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
X
X
Sector Unprotect (
Note 2
)
L
H
L
V
ID
D
IN
X
X
Temporary Sector
Unprotect
X
X
X
V
ID
A
IN
D
IN
D
IN
High-Z
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