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參數(shù)資料
| 型號： | S29AL016D90BAN012 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8.15 X 6.15 MM, FBGA-48 |
| 文件頁數(shù)： | 17/55頁 |
| 文件大小： | 1809K |
| 代理商： | S29AL016D90BAN012 |
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S29AL016D
S29AL016D_00_A7 November 27, 2007
Da ta
Sh e e t
8.1
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 10.1 on page 30 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down transitions, or from system
noise.
8.1.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
8.1.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.1.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
8.1.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
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