參數(shù)資料
型號: S29AL016D70BAI013
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 16 MEGABIT CMOS 3.0 VOLT ONLY BOOT SECTOR FLASH MEMORY
中文描述: 1M X 16 FLASH 3V PROM, 70 ns, PBGA48
封裝: 8.15 X 6.15 MM, FBGA-48
文件頁數(shù): 11/58頁
文件大小: 1037K
代理商: S29AL016D70BAI013
December 17, 2004 S29AL016D_00_A2
S29AL016D
11
P r e l i m i n a r y
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins
to V
IL
. CE# is the power control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
IH
. The BYTE#
pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the com-
mand register contents are altered.
See
Reading Array Data
for more information. Refer to the AC
Read Operations
table for timing specifications and to
Figure 13
for the timing diagram. I
CC1
in the
DC Characteristics table represents the active current specification for reading ar-
ray data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. S ee
Word/Byte Configuration
for more
information.
The device features an
Unlock Bypass
mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four.
Word/Byte Program Command
Sequence
has details on programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables
2
and
3
indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
Command Definitions
section has details on erasing a sector or the entire chip,
or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the
Autoselect Mode
and
Autoselect
Command Sequence
sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for
the write mode. The
AC Characteristics
section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and I
CC
read specifications apply. Refer to
Write Operation Status
for more infor-
mation, and to
AC Characteristics
for timing diagrams.
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