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參數(shù)資料
| 型號： | S25FL002D0FNFI013 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| 中文描述： | 2M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 6 X 5 MM, LEAD FREE, WSON-8 |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 892K |
| 代理商： | S25FL002D0FNFI013 |
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June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
13
P r e l i m i n a r y I n f o r m a t i o n
Instructions
All instructions, addresses, and data are shifted in and out of the device, starting
with the most significant bit. Serial Data Input (SI) is sampled on the first rising
edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one-
byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (SI), each bit being latched on the rising edges of Serial
Clock (SCK). The instruction set is listed in Table
5
.
Every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the in-
struction sequence has been shifted in.
In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read
(FAST_READ) and Read ID (READ_ID), the shifted-in instruction sequence is fol-
lowed by a data-out sequence. Chip Select (CS#) can be driven High after any
bit of the data-out sequence is being shifted out to terminate the transaction.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write
Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc-
tion, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select
(CS#) must driven High when the number of clock pulses after Chip Select (CS#)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle,
Program cycle or Erase cycle are ignored, and the internal Write Status Register
cycle, Program cycle or Erase cycle continues unaffected
Table 5. Instruction Set.
Instruction
Description
One-Byte Instruction
Code
Status Register Operations
06H (0000 0110)
04H (0000 0100)
01H (0000 0001)
05H (0000 0101)
Read Operations
03H (0000 0011)
0BH (0000 1011)
ABH (1010 1011)
Erase Operations
D8H (1101 1000)
C7H (1100 0111)
Program Operations
02H (0000 0010)
Dummy Power Savings Mode Operations
Software Protect
Release from Software Protect
Release from Software Protect and
Read Electronic Signature
Address
Bytes
Dummy
Byte
Data Bytes
WREN
WRDI
WRSR
RDSR
Write Enable
Write Disable
Write to Status Register
Read from Status Register
0
0
0
0
0
0
0
0
0
0
1
1 to Infinity
READ
Read Data Bytes
3
3
0
0
1
3
1 to Infinity
1 to Infinity
1 to Infinity
FAST_READ
READ_ID
Read Data Bytes at Higher Speed
Read ID
SE
BE
Sector Erase
Bulk (Chip) Erase
3
0
0
0
0
0
PP
Page Program
3
0
1 to 256
SP
B9H (1011 1001)
ABH (1010 1011)
0
0
0
0
0
0
RES
ABH (1010 1011)
0
3
1 to Infinity
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