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參數(shù)資料
| 型號(hào)： | S25FL002D0FMFI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| 中文描述： | 2M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, MS-012AA, SO-8 |
| 文件頁數(shù)： | 16/38頁 |
| 文件大小： | 892K |
| 代理商： | S25FL002D0FMFI003 |
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16
S25FL Family (Serial Peripheral Interface)
30167A+1 June 9, 2004
P r e l i m i n a r y I n f o r m a t i o n
WIP bit:
The Write In Progress (WIP) bit indicates whether the memory is busy
with a Write Status Register, Program or Erase cycle. This bit is a read only bit
and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in
progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to
the Status Register. Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select
(CS#) Low, followed by the instruction code and the data byte on Serial Data
Input (SI).
The instruction sequence is shown in
Figure 8
.
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1
and b0 of the Status Register. Bits b6, b5 and b4 are always read as 0.
Chip Select (CS#) must be driven High after the eighth bit of the data byte has
been latched in. If not, the Write Status Register (WRSR) instruction is not exe-
cuted. As soon as Chip Select (CS#) is driven High, the self-timed Write Status
Register cycle (whose duration is t
W
) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. At some un-
specified time before the cycle is completed, the Write Enable Latch (WEL) is
reset.
The Write Status Register (WRSR) instruction allows the user to change the val-
ues of the Block Protect (BP1, BP0) bits, to define the size of the area that is to
be treated as read-only, as defined in Table
1
and Table
2
. The Write Status Reg-
ister (WRSR) instruction also allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the
device to be put in the Hardware Protected Mode (HPM). The Write Status Regis-
ter (WRSR) instruction cannot be executed once the Hardware Protected Mode
(HPM) is entered.
Figure 8. Write Status Register (WRSR) Instruction Sequence
High Impedance
MSB
Instruction
Status
Register In
CS#
SCK
SI
SO
0 1
2 3
4
5 6
7
8 9 10 11 12 13 14 15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S25FL002D0FMFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D0FMFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D0FNAI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D0FNAI003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
| S25FL002D0FNAI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface |
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