參數(shù)資料
型號： S25FL001D0FMFI013
廠商： Spansion Inc.
英文描述： INDUCTOR,STANDARD WOUND,0806,47UH 10% ,T&R RoHS Compliant: Yes
中文描述： 2兆位，1兆閃存的CMOS 3.0伏，25兆赫的SPI總線接口內存
文件頁數(shù)： 19/38頁
文件大?。?/td> 892K
代理商： S25FL001D0FMFI013
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
19
P r e l i m i n a r y I n f o r m a t i o n
(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
Figure 10. Fast Read (FAST_READ) Instruction Sequence
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, three address bytes and at least one data byte
on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Figure 11
.
If more than 256 bytes are sent to the device, the addressing will wrap to the
beginning of the same page, previously latched data are discarded and the last
256 data bytes are guaranteed to be programmed correctly within the same
page. If fewer than 256 Data bytes are sent to device, they are correctly pro-
grammed at the requested addresses without having any effects on the other
bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte
has been latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle
(whose duration is t
PP
) is initiated. While the Page Program cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. At some unspecified time before the cycle is com-
pleted, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page that is protected by the Block
Protect (BP1, BP0) bits (see Table
1
and
Table
2
) is not executed.
CS#
SCK
SI
SO
Instruction
24-Bit
Address
Dummy Byte
High Impedance
DATA OUT 1
DATA OUT 2
MSB
MSB
0
1
2
3
4
5
6
7
8
9
10
28
29 30
31 32 33
34 35 36
37 38
39
40 41
42 43
44
45
46
47
23 22
21
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
相關PDF資料
PDF描述
S25FL001D0FNAI001 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNAI003 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNAI011 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNFI003 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNFI011 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
相關代理商/技術參數(shù)
參數(shù)描述
S25FL001D0FNAI001 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNAI003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNAI011 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNAI013 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
S25FL001D0FNFI001 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
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