參數(shù)資料
型號(hào): S25FL001D0FMAI003
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
中文描述: 1M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, PLASTIC, MS-012AA, SO-8
文件頁(yè)數(shù): 11/38頁(yè)
文件大?。?/td> 892K
代理商: S25FL001D0FMAI003
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
11
P r e l i m i n a r y I n f o r m a t i o n
To enter the Hold condition, the device must be selected, with Chip Select (CS#)
Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal,
provided that this coincides with Serial Clock (SCK) being Low (as shown in
Figure
3
).
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided
that this coincides with Serial Clock (SCK) being Low.
If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold
condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising
edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends
after Serial Clock (SCK) next goes Low (
Figure 3
). During the Hold condition, the
Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial
Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip Select (CS#) driven Low, for the
entire duration of the Hold condition. This ensures that the state of the internal
logic remains unchanged from the moment of entering the Hold condition.
Note: Driving Chip Select (CS#) high while HOLD# is still low is not a
valid operation.
Figure 3. Hold Condition Activation
SCK
HOLD#
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
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