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參數(shù)資料
| 型號(hào)： | S24042 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| 中文描述： | 精密復(fù)位控制器和4K的I2C既復(fù)位和復(fù)位輸出記憶 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 164K |
| 代理商： | S24042 |
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S24042/S24043
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
Sequential READ
Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
S24042/43. The S24042/43 continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
During a sequential read operation, the internal address
counter is automatically incremented with each acknowl-
edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will
‘
roll-over
’
and the
memory will continue to output data. See Figure 9 for the
address, acknowledge and data transfer sequence.
FIGURE 9. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
8
A
8
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Shading Denotes
24042/43
SDA Output Active
S
T
A
R
T
Word Address
S
T
O
P
A
C
K
Acknowledges from 24042/43
Slave Address
Slave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
X
R
W
X
Acknowledge from
Master Receiver
A
C
K
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
1 0 1 0
1 0 1 0
1
0
Slave sends
Data to Master
X X
R
W
Lack of ACK (low)
determines last
data byte to be read
1
Lack of
Acknowledge from
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Last Data Byte
First Data Byte
2011 T fig09 2.0
A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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