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參數資料
| 型號： | S24023SA |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs |
| 中文描述： | 精密復位控制器和4K的I2C既復位和復位輸出記憶 |
| 文件頁數： | 5/14頁 |
| 文件大?。?/td> | 164K |
| 代理商： | S24023SA |
S24042/S24043
5
2011 2.1 8/2/00
SUMMIT MICROELECTRONICS, Inc.
FIGURE 5. PAGE/BYTE WRITE MODE
WRITE OPERATIONS
The S24042/43 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t
WR
). The
page write operation allows up to 16 bytes in the same
page to be written during t
WR
.
Byte WRITE
Upon receipt of the slave address and word address, the
S24042/43 responds with an ACKnowledge. After receiv-
ing the next byte of data, it again responds with an
ACKnowledge. The master then terminates the transfer
by generating a STOP condition, at which time the
S24042/43 begins the internal write cycle.
While the internal write cycle is in progress, the S24042/
43 inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, ACKnowledge and data transfer sequence.
Page WRITE
The S24042/43 is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
bytes of data. After the receipt of each byte, the S24042/
43 will respond with an ACKnowledge.
The S24042/43 automatically increments the address for
subsequent data words. After the receipt of each word,
the low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than 16 bytes,
prior to generating the STOP condition, the address
counter will
“
roll over,
”
and the previously written data will
be overwritten. As with the byte-write operation, all inputs
are disabled during the internal write cycle. Refer to
Figure 5 for the address, ACKnowledge and data transfer
sequence.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to
“
1,
”
a read operation is selected;
when set to
“
0,
”
a write operation is selected.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
8
A
8
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
5
D
6
D
4
D
0
D
3
D
2
D
1
S
T
A
R
T
Word Address
Data Byte n
Data Byte n+15
S
T
O
P
A
C
K
Acknowledges Transmitted from
24042/43 to Master Receiver
Slave Address
Device
Type
Address
Read/Write
0= Write
SDA
Bus
Activity
A
C
K
A
C
K
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
1 0 1 0
0
Data Byte n+1
A
C
K
Master Writes
Data to Slave
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Shading Denotes
24042/43
SDA Output Active
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Master Writes
Data to Slave
Master Writes
Data to Slave
Acknowledges Transmitted from
24042/43 to Master Receiver
If single byte-write only,
Stop bit issued here.
X X
R
W
A
C
K
2011 ILL8 1.0
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