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參數(shù)資料
| 型號： | S2025C-15 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| 封裝： | LDCC-196 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 126K |
| 代理商： | S2025C-15 |
2
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
DATA TRANSFER
For each configured connection between a differential
input pair and an enabled output pair, any data appear-
ing at the input pair will be passed immediately through
to the output pair.
RECONFIGURATION
The S2025 can be selectively reconfigured one output
pair at a time, or any number of output pairs can be
reconfigured simultaneously. Configuration data is
stored in 32 registers, one register for each output pair.
As shown in Figure 1, the configuration data is passed
in parallel from all 32 registers to a latch which holds the
active switch configuration. This two-stage arrange-
ment allows one or more output pairs to be reconfigured
simultaneously.
Each configuration register in the configuration Regis-
ter File (CRF) holds 6 bits. Five bits are used to select
which input pair will be connected to the output pair and
one bit is used to enable or disable the output pair driver.
To connect an output pair to a given input pair, the
output pair to be reconfigured is selected using bits
OADDR0-4 of the OA register. These bits are set using the
OADDR and OACLK inputs. The OACLK input, with 100
MHz maximum frequency, can load the OA shift register
through the OADDR input, with the OADDR4 (MSB)
entering first, followed by the OADDR3, and so on. With
the configuration register selected, the desired input
selection is provided on the bits IADDR0-4 of the IA
register. Whether or not the output pair is to be enabled
is provided on the bit IADDR5 (1= enable, 0 = disable)
of the same register. The bits IADDR0-5 are set using
the IADDR and IACLK inputs. The IACLK input, with
100 MHz maximum frequency, can load the IA shift
register through the IADDR input, with the IADDR5
entering first, followed by the IADDR4 (MSB), and so
on. The IADDR0-5 information will be stored into the
selected configuration register by the LOADN strobe.
When the differential switch is to be reconfigured, the
S2025 minimizes the time required through the use of an
active configuration latch. While the switch is operational,
and prior to the time at which it must be reconfigured, a
new configuration can be loaded into the output pair
configuration registers. Once the 32 output pair configu-
ration registers contain the desired connection and
output pair driver enable information, the contents of the
registers are transferred in parallel to the active configu-
ration latch by the CONFIGN strobe. This allows multiple
connections to be simultaneously changed.
The configuration latch can be made transparent by
tying the CONFIGN input to a logic 0. When this is done,
changes strobed into the output pair configuration reg-
isters by the LOADN input pair will be passed immediately
to the switch.
Figure 2. Data Transfer Waveforms
tCFDO
tLDDO
tDIDO
DIMPW
DINO-31 P/N
DOUTO-31 P/N
CONFIGN
LOADN
A
AB
C
D
E
BC
DE
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| S2025L | 制造商:Littelfuse 功能描述:SCR Thyristor |
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