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參數(shù)資料
| 型號： | S1R72V27B05 |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 42/42頁 |
| 文件大?。?/td> | 426K |
| 代理商： | S1R72V27B05 |
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4. Explanation of Functions
4
EPSON
S1R72V27 Data Sheet (Rev. 1.00)
4. Explanation of Functions
For details of the register names used in the following discussion, refer to the Technical Manual for this LSI.
4.1
Power Supply
This LSI has three power supply systems and a common GND. The power supply systems consist of
HVDD (3.3 V) for the USB I/O power supply, CVDD (3.3 V to 1.8 V) for the CPU I/F power supply,
and LVDD (1.8 V) for internal circuits and TEST I/O. (See Figure 4-1.)
I
O
CPU
-I/F
FIFO
SIE
MTM
CPU
USB
LVDD
HVDD
CVDD
1.8V to 3.3V
1.8V
3.3V
TEST
IO
Figure 4-1 S1R72V27 power supply circuit diagram
The sequence of steps for turning the power supplies on and off are described below.
This LSI cannot be operated with only the LVDD or CVDD power supplies turned on or off. The
HVDD can be turned off if the LVDD or CVDD power supplies are on. The synchronous register
cannot be accessed while HVDD is off, since the PLL does not operate.
Also, the following restrictions apply to the sequence for turning the CVDD/HVDD I/O power
supplies and LVDD internal power supply on or off. There are no restrictions on the sequence for
turning the CVDD and HVDD power supplies on or off.
The LVDD must be turned on before turning on the CVDD and HVDD power supplies.
In the powering off sequence, the CVDD and HVDD must be turned off before turning off the
LVDD.
If power supply circuit characteristics or the power supply load make this sequence impossible to
follow, the CVDD or HVDD must not be on for more than 1 second while the LVDD is off.
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