參數(shù)資料
型號: S1L52502
廠商: 愛普生(中國)有限公司
英文描述: HIGH DENSITY GATE ARRAY
中文描述: 高密度門陣列
文件頁數(shù): 10/12頁
文件大?。?/td> 105K
代理商: S1L52502
10
EPSON ELECTRONICS AMERICA, INC.
i
150 River Oaks Pkwy
i
San Jose, CA 95134
i
Tel: (408) 922-0200
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Fax: (408) 922-0238
ASIC
S1L50000
DATA SHEET
EEA CUSTOMER ENGINEERING
To help customers implement their design of EEA ASIC’s, we offer training at our design centers
and at customer sites when required.
When a design is started, an EEA engineer is assigned to the project and will remain with the
project through its completion. EEA engineers will work with the customer on design, software and
other technical issues. When the design files are transferred to EEA, the assigned engineer will
verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering
Group provides all technical customer-support services including:
Pre-Sale Technical Support
Customer Training
Design Assistance
Custom Cell Development
Place and Route
Scan Insertion and ATPG
Netlist Conversion and Synthesis
EDA/CAE SUPPORT
Software Documentation
Simulation Support
Turnkey Design
Design Verification
Static Timing Analysis
JTAG Insertion
Test Vector Conversion
Schematic Capture
Viewlogic (Synopsys): Viewdraw
EEA: Auklet (ECS)
Synthesis
Synopsys: DesignCompiler
Exemplar Logic: Leonardo
Simulation
Cadence: Verilog-XL
Synopsys: VSS (VHDL)
Avant!: Polaris (Purespeed)
Viewlogic (Synopsys): Viewsim
Modeltech: V-System (VHDL)
DFT
Synopsys: TestCompiler+
Viewlogic (Synopsys): TestGen (Sunrise)
Place & Route
Cadence: GateEnsemble
Avant!: Aquarius-GA (Apollo)
Delay Calculation (Post-Route)
EEA: Peacock (EXDT)
相關(guān)PDF資料
PDF描述
S1L52503 HIGH DENSITY GATE ARRAY
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