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參數(shù)資料
| 型號： | S1L50754 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | HIGH DENSITY GATE ARRAY |
| 中文描述： | 高密度門陣列 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 105K |
| 代理商： | S1L50754 |
2
EPSON ELECTRONICS AMERICA, INC.
i
150 River Oaks Pkwy
i
San Jose, CA 95134
i
Tel: (408) 922-0200
i
Fax: (408) 922-0238
ASIC
S1L50000
DATA SHEET
LINE UP
The
S1L50000
Series comprises 11 types of masters, from which the customer is able to select
the master most suitable.
Cell Utilization Ratio (U)
*1
2-layer
metal
metal
50%
88%
47%
85%
47%
85%
45%
80%
45%
75%
45%
75%
43%
75%
40%
70%
40%
70%
40%
70%
40%
70%
Master
Total
BC
(Raw Gates)
Number
of
Pads
88
144
168
188
224
264
308
352
376
432
480
Number
of
Columns (X)
319
519
594
669
794
944
1094
1256
1344
1544
1706
Number
of
Rows (Y)
90
146
167
188
223
265
307
352
377
433
478
3-layer
4-layer
metal
95%
95%
95%
95%
95%
95%
95%
90%
90%
90%
90%
S1L50282/283/284 28710
S1L50752/753/754 75774
S1L50992/993/994 99198
S1L51252/253/254 125772
S1L51772/773/774 177062
S1L52502/503/504 250160
S1L53352/353/354 335858
S1L54422/423/424 442112
S1L55062/063/064 506688
S1L56682/683/684 668552
S1L58152/153/154 815468
NOTE:
1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
相關PDF資料 |
PDF描述 |
|---|---|
| S1L50992 | HIGH DENSITY GATE ARRAY |
| S1L50993 | HIGH DENSITY GATE ARRAY |
| S1L50994 | HIGH DENSITY GATE ARRAY |
| S1L51252 | HIGH DENSITY GATE ARRAY |
| S202C22TSWCDQE | Slide Switches |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S1L50992 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L50993 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L50993F22R200 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON ASICS GATE ARRAYS |
| S1L50994 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L51252 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
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