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參數(shù)資料
| 型號(hào)： | S1L50752 |
| 廠商： | 愛(ài)普生（中國(guó)）有限公司 |
| 英文描述： | HIGH DENSITY GATE ARRAY |
| 中文描述： | 高密度門(mén)陣列 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | S1L50752 |
6
EPSON ELECTRONICS AMERICA, INC.
i
150 River Oaks Pkwy
i
San Jose, CA 95134
i
Tel: (408) 922-0200
i
Fax: (408) 922-0238
ASIC
S1L50000
DATA SHEET
Electrical Characteristics of the
S1L50000
Series:
(V
DD
= 5.0V, V
SS
= 0V, T
a
= -40 to 85
°
C)
Item
Symbol
I
LI
I
OZ
V
OH
Conditions
Min
-1
-1
HV
DD
-0.4
Typ
--
--
--
Max
1
1
--
Unit
μ
A
μ
A
V
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
--
--
I
OH
= -0.1mA (Type S), -1mA (Type M),
-3mA (Type 1), -8mA (Type 2), -12mA
(Type 3, Type 4)
V
DD
= Min
I
OL
= 0.1mA (Type S), 1mA (Type M),
3mA (Type 1), 8mA (Type 2), 12mA
(Type 3), 24mA (Type 4)
V
DD
= Min
CMOS Level, HV
DD
= Max
CMOS Level, HV
DD
= Min
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
TTL Level, HV
DD
= Max
TTL Level, HV
DD
= Min
TTL Schmitt
TTL Schmitt
TTL Schmitt
PCI Level, HV
DD
= Max
PCI Level, HV
DD
= Min
PCI Response,
V
OH
= 1.4V, HV
DD
= Min
V
OH
= 3.1V, HV
DD
= Max
PCI Response
V
OH
= 2.20V, HV
DD
= Min
V
OL
= 0.71V, HV
DD
= Max
V
I
= 0V
Low Level Output Voltage
V
OL
--
--
0.4
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
V
IH1
V
IL1
V
T1+
V
T1-
V
H1
V
IH2
V
IL2
V
T2+
V
T2-
V
H2
V
IH3
V
IL3
I
OH3
3.5
--
2.0
0.8
0.3
2.0
--
1.2
0.6
0.1
2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1.0
4.0
3.1
--
--
0.8
2.4
1.8
--
--
0.8
V
V
V
V
V
V
V
V
V
V
V
V
-44
--
--
--
--
-142
mA
mA
Low Level Output Current
I
OL3
95
--
30
--
--
60
--
206
(120)
144
(240)
288
(120)
144
(240)
288
-80
mA
mA
Type 1
Pull-up Resistance*
R
PU
Type 2
60
120
K
Type 1
30
60
Pull-down Resistance*
R
PD
V
I
= V
DD
Type 2
60
120
K
High Level Maintenance Current
I
BHH
Bus Hold Response, V
IN
= 2.0V
(TTL) HV
DD
= Min
Bus Hold Response, V
IN
= 0.8V
(TTL) HV
DD
= Min
Bus Hold Response, V
IN
= 0.8V
(TTL) HV
DD
= Max
Bus Hold Response, V
IN
= 2.0V
(TTL) HV
DD
= Max
f = 1Mhz, V
DD
= 0V
f = 1Mhz, V
DD
= 0V
f = 1Mhz, V
DD
= 0V
--
--
μ
A
Low Level Maintenance Current
I
BHL
--
--
33
μ
A
High Level Reversal Current
I
BHHO
-550
--
--
μ
A
Low Level Reversal Current
I
BHLO
330
--
--
μ
A
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
The values in parentheses are for the case of T
a
= 0 to 70
°
C.
C
I
C
O
C
IO
--
--
--
--
--
--
10
10
10
pF
pF
pF
*
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PDF描述 |
|---|---|
| S1L50753 | HIGH DENSITY GATE ARRAY |
| S1L50754 | HIGH DENSITY GATE ARRAY |
| S1L50992 | HIGH DENSITY GATE ARRAY |
| S1L50993 | HIGH DENSITY GATE ARRAY |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| S1L50753 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L50754 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L50992 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
| S1L50993 | 制造商:EPSON 制造商全稱:EPSON 功能描述:HIGH DENSITY GATE ARRAY |
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