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參數(shù)資料
| 型號(hào)： | S1D15E06D03E000 |
| 廠商： | 愛(ài)普生（中國(guó)）有限公司 |
| 英文描述： | Direct RAM data display by display data RAM |
| 中文描述： | RAM數(shù)據(jù)顯示直接由顯示數(shù)據(jù)RAM |
| 文件頁(yè)數(shù)： | 11/74頁(yè) |
| 文件大?。?/td> | 490K |
| 代理商： | S1D15E06D03E000 |
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S1D15E06 Series
8
EPSON
Rev. 2.1
P/S
HIGH
LOW
Data/Command
A0
A0
Data
D0 to D7
SI (D7)
Read/Write Serial clock
RD, WR
Write only
SCL (D6)
5.3 System Bus Connection Pin
Pin name
I/O
Description
Number of
pins
8
D7 to D0
I/O
Connects to the 8-bit or 16-bit MPU data bus via the 8-bit
bi-directional data bus.
When the serial interface is selected (P/S = LOW), D7 serves as the
serial data input (SI) and D6 serves as the serial clock input (SCL),
In this case, D0 through D5 go to a high impedance state. When the
Chip select is inactive, D0 through D7 go to a high impedance state.
Normally, the least significant bit MPU address bus is connected
to distinguish between data and command.
A0 =
HIGH : indicates that D0 to D7 are display data or command parameters.
A0 = LOW : indicates that D0 to D7 are control commands.
When the RES is LOW, initialization is achieved.
Resetting operation is done on the level of the RES signal.
A chip select signal. When CS1 = LOW and CS2 = HIGH, signals
are active, and data/command input/output are enabled.
When the 80 series MPU is connected.
A pin for connection of the RD signal of the 80 series MPU.
When this signal is LOW, the data bus of the S1D15E06 series
is in the output state.
When the 68 series MPU is connected.
Serves as a 68 series MPU enable clock input pin.
When the 80 series MPU is connected.
A pin for connection of the WR signal of the 80 series MPU.
Signals on the data bus are latched at the leading edge of the
WR signal.
Serves as a read/write control signal input pin when the 68 series
MPU is connected.
R/W = HIGH : Read
R/W = LOW : Write
A MPU interface switching pin.
C86 = HIGH : 68 series MPU interface
C86 = LOW : 80 series MPU interface
Parallel data input/serial data input select pin
P/S = HIGH : Parallel data input
P/S = LOW : Serial data input
The following Table shows the summary:
(SI)
(SCL)
A0
I
1
RES
I
1
CS1
CS2
RD
(E)
I
2
I
1
WR
(R/W)
I
1
C86
I
1
P/S
I
1
When P/S = LOW, D0 to D5 are high impedance.
D0 to D5 can be HIGH, LOW or open.
RD(E) and WR(R/W) are locked to HIGH or LOW.
The serial data input does not allow the RAM display data to be read.
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