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參數(shù)資料
| 型號： | S1D15E06D01E000 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | Direct RAM data display by display data RAM |
| 中文描述： | RAM數(shù)據(jù)顯示直接由顯示數(shù)據(jù)RAM |
| 文件頁數(shù)： | 62/74頁 |
| 文件大小： | 490K |
| 代理商： | S1D15E06D01E000 |
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S1D15E06 Series
Rev. 2.1
EPSON
59
Table 10.1.2
Table 10.1.3
Parameter
Signal
Symbol
Condition
Specified value
Min.
0
0
400
600
100
250
140
250
40
20
—
10
Unit
Max.
—
—
—
—
—
—
—
—
—
—
200
200
Address hold time
Address setup time
System write cycle time
System read cycle time
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
*1. This is in case of making the access by WR and RD, setting the CS1 = LOW.
*2. This is in case of making the access by CS1, setting the WR, RD = LOW.
*3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed,
it is specified by (
t
r +
t
f
)
≤
(
t
CYC8
–
t
CCLW
–
t
CCHW
) or (
t
r +
t
f)
≤
(
t
CYC8
–
t
CCLR
–
t
CCHR
).
*4. Timing is entirely specified with reference to 20% or 80% of V
DD
.
*5.
t
CCLW
and
t
CCLR
are specified in terms of the overlapped period when CS1 is at LOW (CS2 = HIGH) level and
WR and RD are at LOW level.
A0
t
AH8
t
AW8
t
WCYC8
t
RCYC8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
ACC8
t
OH8
ns
WR
RD
WR
RD
WR
RD
D0 to D7
C
L
=100pF
[V
DD
= 1.7V to 2.4V, Ta =
–
40 to +85
°
C]
Parameter
Signal
Symbol
Condition
Specified value
Min.
0
0
300
400
80
200
80
200
30
15
—
10
Unit
Max.
—
—
—
—
—
—
—
—
—
—
120
120
Address hold time
Address setup time
System write cycle time
System read cycle time
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
A0
t
AH8
t
AW8
t
WCYC8
t
RCYC8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
ACC8
t
OH8
ns
WR
RD
WR
RD
WR
RD
D0 to D7
C
L
=100pF
[V
DD
= 2.4V to 3.0V, Ta =
–
40 to +85
°
C]
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