
S1C6S3N7 TECHNICAL SOFTWARE
EPSON
II-65
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
I/O Port
– When the I/O port is set to the output mode and a low-
impedance load is connected to the port pin, the data
written to the register may differ from the data read.
– When the I/O port is set to the input mode and a low-
level voltage (VSS) is input by the built-in pull-down
resistance, an erroneous input results if the time con-
stant of the capacitive load of the input line and the
built-in pull-down resistance load is greater than the
read-out time. When the input data is being read, the
time that the input line is pulled down is equivalent to
0.5 cycles of the CPU system clock.
Hence, the electric potential of the pins must settle
within 0.5 cycles. If this condition cannot be met, some
measure must be devised, such as arranging a pull-down
resistance externally, or performing multiple read-outs.
LCD Driver
– Because the display memory is for writing only, re-
writing the contents with computing instructions (e.g.,
AND, OR, etc.) which come with read-out operations is
not possible. To perform bit operations, a buffer to hold
the display data is required on the RAM.
– Even when 1/2 duty is selected, the display data corre-
sponding to COM0, COM3 are valid for static drive.
Hence, for static drive set the same value to all display
memory corresponding COM0–COM3.
– Even when 1/3 duty is selected, the display data corre-
sponding to COM3 is valid for static drive. Hence, for
static drive set the same value to all display memory
corresponding COM0–COM3.
– For cadence adjustment, set the display data including
display data corresponding to COM3.
– fosc indicates the oscillation frequency of the oscillation
circuit.
Since supply voltage detection is automatically performed
by the hardware every 2 Hz (0.5 sec) when the heavy load
protection function operates, do not permit the operation
of the SVD circuit by the software in order to minimize
power current consumption.
Supply Voltage Detec-
tion (SVD) Circuit