
I-56
EPSON
S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Timer data (0E4H)
The 16 Hz to 2 Hz timer data of the clock timer can be read
from this register. These four bits are read-only, and write
operations are invalid.
After an initial reset, the timer data is initialized to 0H.
Interrupt mask registers (0EBH D0–D2)
These registers are used to mask the clock timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading:
Valid
The interrupt mask register bits (EIT32, EIT8, EIT2) mask
the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).
Writing to the interrupt mask registers should be done only
in the DI status. Otherwise, it causes malfunction.
After an initial reset, these registers are all set to 0.
Interrupt factor flags (0EFH D0–D2)
These flags indicate the status of the clock timer interrupt.
When 1 is read:
Interrupt has occurred
When 0 is read:
Interrupt has not occurred
Writing:
Invalid
The interrupt factor flags (IT32, IT8, IT2) correspond to the
clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can
determine from these flags whether there is a clock timer
interrupt. However, even if the interrupt is masked, the
flags are set to 1 on the falling edge of the signal. These
flags can be reset when the register is read by the software.
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
After an initial reset, these flags are set to 0.
TM0–TM3
EIT32, EIT8, EIT2
IT32, IT8, IT2