
1
OUTLINE
S1C33209/221/222 PRODUCT PART
EPSON
A-7
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
#CE4
#CE11
63
60
O
–
#CE4:
Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"
(default)
#CE11:
Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.
#CE3
120
117
O
–
Area 3 chip enable
#RD
56
53
O
–
Read signal
#EMEMRD
78
75
O
–
Read signal for internal ROM emulation memory
#WRL
#WR
#WE
58
55
O
–
#WRL:
Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#WR:
Write signal when SBUSST(D3/0x4812E) = "1"
#WE:
DRAM write signal
#WRH
#BSH
59
56
O
–
#WRH:
Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#BSH:
Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"
#HCAS
80
77
O
–
#HCAS:
DRAM column address strobe (high byte) signal
#LCAS
82
79
O
–
#LCAS:
DRAM column address strobe (low byte) signal
BCLK
7
4
O
–
Bus clock output
P34
#BUSREQ
#CE6
69
66
I/O
–
P34:
I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6:
Area 6 chip enable when CFP34(D4/0x402DC) = "1" and
IOC34(D4/0x402DE) = "1"
P35
#BUSACK
49
46
I/O
–
P35:
I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1"
P30
#WAIT
#CE4&5
64
61
I/O
–
P30:
I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT:
Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5:
Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and
IOC30(D0/0x402DE) = "1"
P20
#DRD
117
114
I/O
–
P20:
I/O port when CFP20(D0/0x402D8) = "0" (default)
#DRD:
DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1"
P21
#DWE
#GAAS
119
116
I/O
–
P21:
I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF)
= "0" (default)
#DWE:
DRAM read signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"
#GAAS:
Area address strobe for GA when CFEX2(D2/0x402DF) = "1"
P31
#BUSGET
#GARD
14
11
I/O
–
P31:
I/O port when CFP31(D1/0x402DC) = "0" and
CFEX3(D3/0x402DF) = "0" (default)
#BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1"
and CFEX3(D3/0x402DF) = "0"
#GARD:
Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
EA10MD1
113
110
I
Pull-up Area 10 boot mode selection
EA10MD1
EA10MD0
Mode
1
External ROM mode
EA10MD0
112
109
I
–
1
0
Internal ROM mode
0
1
OTP mode
0
Internal ROM emulation mode