
1
OUTLINE
S1C33209/221/222 PRODUCT PART
EPSON
A-11
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
P26
TM4
SOUT2
4
1
I/O
–
P26:
I/O port when CFP26(D6/0x402D8) = "0" (default)
TM4:
16-bit timer 4 output when CFP26(D6/0x402D8) = "1"
SOUT2:
Serial I/F Ch.2 data outputwhen SSOUT2(D1/0x402DB) = "1" and
CFP26(D6/0x402D8) = "0"
P27
TM5
SIN2
6
3
I/O
–
P27:
I/O port when CFP27(D7/0x402D8) = "0" (default)
TM5:
16-bit timer 5 output when CFP27(D7/0x402D8) = "1"
SIN2:
Serial I/F Ch.2 data input when SSIN2(D0/0x402DB) = "1" and
CFP27(D7/0x402D8) = "0"
Table 1.3.5
List of Pins for Clock Generator
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
OSC1
54
51
I
–
Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock
input)
OSC2
52
49
O
–
Low-speed (OSC1) oscillation output
OSC3
118
115
I
–
High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock
input)
OSC4
116
113
O
–
High-speed (OSC3) oscillation output
PLLS[1:0]
108,109
105,106
I
–
PLL set-up pins
PLLS1
PLLS0
fin (fOSC3)
fout (fPSCIN)
1
10–30MHz
20–60MHz
*1
10–25MHz
20–50MHz
*2
0
1
10–15MHz
40–60MHz
*1
10–12.5MHz
40–50MHz
*2
0
PLL is not used
L
*1: ROM-less model with 3.3 V
± 0.3 V operating voltage
*2: ROM built-in model, or 3.0 V
± 0.3 V operating voltage
PLLC
106
103
–
Capasitor connecting pin for PLL
Table 1.3.6
List of Other Pins
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
/down
ICEMD
98
95
I
Pull-
down
High-impedance control input pin
When this pin is set to High, all the outputpins go into high-impedance state. This
makes it possible to disable the S1C33 chip on the board.
DSIO
123
120
I/O
Pull-up Serial I/O pin for debugging
This pin is used to communicate with the debugging tool S5U1C33000H.
#X2SPD
111
108
I
–
Clock doublingmode set-uppin1: CPU clock = bus clock
× 1, 0: CPU clock = bus
clock
× 2
#NMI
66
63
I
Pull-up NMI request input pin
#RESET
65
62
I
Pull-up Initial reset input pin
Note: "#" in the pin names indicates that the signal is low active.