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參數(shù)資料
| 型號(hào)： | S1703C-FREQ1-OUT29 |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1.8432 MHz - 67 MHz, HCMOS/TTL OUTPUT |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 100K |
| 代理商： | S1703C-FREQ1-OUT29 |
SaRonix
Crystal Clock Oscillator
3.3 & 5V, HCMOS, TTL, SMD
S1700 / S1703 / S1750 Series
Technical Data
DS-138
REV G01
All specifications are subject to change without notice.
Tri-State Logic Table
Test Circuit
Recommended Land Pattern
Scale: None (Dimensions in
)
mm
inches
POWER
SUPPLY
mA
M
V M
TEST
POINT
OUT
VCC
OSCILLATOR
GND
Pad 2
Pad 1
Pad 4
Pad 3
0.1F
CL = 15 / 30 /50 pF
(Note A)
TRI-STATE INPUT
Note A: CL includes probe and fixture capacitance
15 pF S1700 to 80 MHz
30 pF S1703 to 67 MHz (for higher frequencies, please contact SaRonix)
50 pF S1750 to 67 MHz
TTL
LOGIC 1
50% VDD
20% VDD
LOGIC 0
80% VDD
SYMMETRY
Tf
Tr
GND
VDD
Tf
Tr
CMOS
Output Waveform
Pad 1 Input
Logic 1 or NC
Logic 0 or GND
Pad 3 Output
Oscillation
High Impedance
5.2
.205
max
7.2
.284
max
1.7
.067
Pad 1
(Tri-State
Control)
Pad 2
(GND)
Pad 4
(VCC)
Pad 3
(OUT)
1.4
.055
1.2
.047
2.6
.102
5.08
.200
Date Code
Frequency
SaRonix
S 2 C
B = ±50 ppm
C = ±100 ppm
2 = S1700
3 = S1703
7 = S1750
Marking Format
Package Details
Required Input Levels on Pad 1:
90% VDD min
10% VDD max
YY WW
SYMMETRY
2.5 VDC
1.5 VDC
0.5 VDC
1.8
.071
2.0
.079
4.2
.165
5.08
.200
*External power supply decoupling required.
*
12
43
SaRonix
141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
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