參數(shù)資料
型號： S12EETS2KV1D
廠商： Motorola, Inc.
英文描述： MC9S12DT128 Device User Guide V02.09
中文描述： MC9S12DT128設(shè)備的用戶手冊V02.09
文件頁數(shù)： 75/138頁
文件大?。?/td> 2083K
代理商： S12EETS2KV1D
MC9S12DT128 Device User Guide — V02.09
75
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1
shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
Figure 3-1 Clock Connections
CRG
bus clock
core clock
EXTAL
XTAL
oscillator clock
HCS12 CORE
IIC
RAM
SCI0, SCI1
PWM
ATD0, 1
BF
Flash
ECT
BDLC
SPI0, 1
CAN0, 1, 4
PIM
EEPROM
BDM
MEBI
INT
CPU
BKP
MMC
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S12IICV2 MC9S12DT128 Device User Guide V02.09
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