參數(shù)資料
型號: S-812C26AY-Z
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: 2.6 V FIXED POSITIVE LDO REGULATOR, 0.68 V DROPOUT, PBCY3
封裝: TO-92, 3 PIN
文件頁數(shù): 6/49頁
文件大?。?/td> 873K
代理商: S-812C26AY-Z
HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR
S-812C Series
Rev.2.0_01
14
Seiko Instruments Inc.
Description of Operation
1. Basic Operation
Figure 15 shows the block diagram of the S-812C series. The error amplifier compares a reference
voltage (Vref) with a part of the output voltage divided by the feedback resistors Rs and Rf, and supplies
the gate voltage to the output transistor, necessary to ensure certain output voltage independent from
change of input voltage and temperature.
Reference
voltage
circuit
VOUT
*1
VSS
VIN
RS
Rf
Error amplifier
Current sauce
Vref
+
*1. Parasitic diode
Figure 15
2. Output Transistor
The S-812C Series uses a Pch MOS FET as the output transistor.
The voltage at VOUT must not exceed VIN+0.3V. When the VOUT voltage becomes higher than that of VIN,
reverse current flows and may break the regulator since a parasitic diode between VOUT and VIN pins
exists inevitably.
相關(guān)PDF資料
PDF描述
S-812C28AY-B 2.8 V FIXED POSITIVE LDO REGULATOR, 0.68 V DROPOUT, PBCY3
S-812C44AUA-C2Y-T2 4.4 V FIXED POSITIVE LDO REGULATOR, 0.3 V DROPOUT, PSSO3
S-812C47AUA-C3B-T2 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PSSO3
S-812C51AY-B 5.1 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PBCY3
S-812C53AMC-C3H-T2 5.3 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PDSO5
相關(guān)代理商/技術(shù)參數(shù)
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