參數(shù)資料
型號(hào): S-80826
廠(chǎng)商: Seiko Instruments Inc.
英文描述: 2.6 V±2.0% Super-Small Package High-Precision Voltage Detector(微型封裝,檢測(cè)范圍2.6 V±2.0%,高精度電壓檢測(cè)器)
中文描述: 為2.6 V ± 2.0%,超小型封裝高精度電壓檢測(cè)器(微型封裝,檢測(cè)范圍為2.6 V ± 2.0%,高精度電壓檢測(cè)器)
文件頁(yè)數(shù): 15/36頁(yè)
文件大?。?/td> 308K
代理商: S-80826
SUPER-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR
S-808 Series
14
Seiko Instruments Inc.
Operation
1.
Basic operation : CMOS active low output
(1) When power supply voltage V
DD
is greater than the release voltage +V
DET
, the Nch transistor is OFF and the Pch
transistor ON, causing V
DD
(high) to appear at the output. With the Nch transistor N1 of Figure 9 OFF, the comparator
input voltage is (RB+RC)/(RA+RB+RC)
×
V
DD
.
(2) When power supply voltage V
DD
goes below +V
DET
, the output maintains the power supply voltage level, as long as V
DD
remains above the detection voltage -V
DET
. When V
DD
does fall below -V
DET
(A in Figure 10), the Nch transistor goes ON,
the Pch transistor goes OFF, and V
SS
appears at the output. With the Nch transistor N 1 of Figure 9 ON, the comparator
input voltage is RB/(RA+RB)
×
V
DD
.
(3) When V
DD
falls below the minimum operating voltage, the output becomes undefined. However, output will revert to V
DD
if a pull-up has been employed.
(4) V
SS
will again be output when V
DD
rises above the minimum operating voltage. V
SS
will continue to be output even when
V
DD
surpasses -V
DET
, as long as it does not exceed the release voltage +V
DET
.
(5) When V
DD
rises above +V
DET
(B in Figure 10), the Nch transistor goes OFF, the Pch transistor goes ON, and V
DD
appears at the output.
A
B
V
D
Release voltage (+V
DET
)
Detection voltage (-V
DET
)
V
SS
Min. operating voltage
OUT terminal output
Hysteresis
width (V
HYS
)
V
D
V
SS
(1)
(2)
(3)
(5)
(4)
+
V
REF
RA
R
RC
N1
V
S
V
DD
Figure 9
*
OUT
*
Pch
Nch
Figure 10
*
Parasitic diode
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