參數(shù)資料
型號: S-35L32AEFSG
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: REAL TIME CLOCK, PDSO10
封裝: 0.50 MM PITCH, PLASTIC, SSOP-10
文件頁數(shù): 18/37頁
文件大?。?/td> 502K
代理商: S-35L32AEFSG
REAL-TIME CLOCK
Rev.1.3_00
S-35L32A
Seiko Instruments Inc.
25
6. Power voltage detecting circuit
S-35L32A has an internal power voltage detecting circuit. This circuit gives sampling movement for only
15.6 ms once a second. If the power voltage decreases below the detection voltage (VDET), the BLD latch
circuit latches the “H” level, and sampling movement stops. Only when subsequent communication is of the
status read command, the output of the latch circuit is transferred to the sift register and the sampling
movement is resumed. The decrease in power voltage can be monitored in reading the POWER flag. That is
to say, once it is detected, any detecting operation is not performed and "H" is held unless you perform
initialization or send the status read command.
Caution
When power voltage is increased and the first read operation is performed after decrease in
power voltage occurs and the latch circuit latches "H", "1" can be read on the POWER flag,
however, if the next read operation is performed after the sampling of the detecting circuit,
the POWER flag is reset since sampling is subsequently allowed. See the timing diagram
below.
Latch circuit output
Sampling pulse
(0)
1s
Stop
(1)
(1) (1)
(1)
(0)
POWER flag
VDD
VDET
Communication
Latch circuit
output
Sampling pulse
1 s
(1)
(0)
Communication
POWER flag
Carry pulse
[Timing of sampling pulse]
0.5 s
7.8 ms
Carry-up timing
1 Hz
15.6 ms
Latch timing
Sampling pulse
(1)
(0)
VDET
VDD
Stop
Figure 20 Timing of the power voltage detecting circuit
DISCONTINUED
PRODUCT
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