參數(shù)資料
型號(hào)： S-35399A03-J8T2G
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝： LEAD FREE, SOP-8
文件頁(yè)數(shù)： 33/53頁(yè)
文件大?。?/td> 472K
代理商： S-35399A03-J8T2G
2-WIRE REAL-TIME CLOCK
Rev.2.0_00
S-35399A03
Seiko Instruments Inc.
39
Reset After Communication Interruption
In case of communication interruption in the S-35399A03, for example, during communication the power supply voltage
drops so that only the master device is reset; the S-35399A03 does not operate the next procedure because the internal
circuit keeps the state prior to interruption. The S-35399A03 does not have a reset pin so that users usually reset its internal
circuit by inputting a stop condition. However, if the SDA line is outputting “L” (during output of acknowledgment signal or
Read), the S-35399A03 does not accept a stop condition from the master device. In this case, users are necessary to finish
acknowledgment output or Read the SDA line. Figure 49 shows how to reset. First, input a start condition from the master
device (The S-35399A03 cannot detect a start condition because the SDA line in the S-35399A03 is outputting “L”). Next,
input a clock pulse equivalent to 1-byte data access (9-clock) from the SCL line. During this, release the SDA line for the
master device. By this procedure, SDA I/O before interruption is finished, so that the SDA line in the S-35399A03 is
released. After that, inputting a stop condition resets the internal circuit so that restore the regular communication. This
reset procedure is recommended to perform at initialization of the system after rising the master device’s power supply
voltage.
12
8
9
SCL
SDA
(Output from
master device)
Stop condition
Clocks equivalent to 1-byte data access
SDA
(Output from
S-35399A03)
Start
condition
“L” or High-Z
“L”
High-Z
“L”
High-Z
SDA
“L” or High-Z
Figure 49 How to Reset
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