參數(shù)資料
型號: S-35392A-I8T1U
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: HALOGEN FREE AND LEAD FREE, SNT-8
文件頁數(shù): 28/47頁
文件大小: 419K
代理商: S-35392A-I8T1U
2-WIRE REAL-TIME CLOCK
S-35392A
Rev.2.0_00
Seiko Instruments Inc.
34
Reset After Communication Interruption
In case of communication interruption in the S-35392A, for example, during communication the power supply voltage
drops so that only the master device is reset; the S-35392A does not operate the next procedure because the internal
circuit keeps the state prior to interruption. The S-35392A does not have a reset pin so that users usually reset its internal
circuit by inputting a stop condition. However, if the SDA line is outputting “L” (during output of acknowledgment signal or
Read), the S-35392A does not accept a stop condition from the master device. In this case, users are necessary to finish
acknowledgment output or Read the SDA line. Figure 41 shows how to reset. First, input a start condition from the master
device (The S-35392A cannot detect a start condition because the SDA line in the S-35392A is outputting “L”). Next, input
a clock pulse equivalent to 7-byte data access (63-clock) from the SCL line. During this, release the SDA line for the
master device. By this procedure, SDA I/O before interruption is finished, so that the SDA line in the S-35392A is released.
After that, inputting a stop condition resets the internal circuit so that restore the regular communication. This reset
procedure is recommended to perform at initialization of the system after rising the master device’s power supply voltage.
1
2
62
63
8
9
Start
condition
Stop
condition
Clocks equivalent to 7-byte data access
SCL
“L”
“L” or High-Z
High-Z
SDA
(Output from
master device)
SDA
(Output from
S-35392A)
SDA
“L” or High-Z
“L”
Figure 41
How to Reset
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