參數(shù)資料
型號: S-35390A-J8T1G
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: LEAD FREE, SOP-8
文件頁數(shù): 22/56頁
文件大?。?/td> 529K
代理商: S-35390A-J8T1G
2-WIRE REAL-TIME CLOCK
Rev.3.0_00
S-35390A
Seiko Instruments Inc.
29
Serial Interface
The S-35390A receives various commands via I
2C-bus serial interface to Read/Write data. Regarding transmission is as
follows.
1.
Start condition
A start condition is when the SDA line changes “H” to “L” when the SCL line is in “H”, so that the access starts.
2.
Stop condition
A stop condition is when the SDA line changes “L” to “H” when the SCL line is in “H”, and the access stops, so that the
S-35390A gets standby.
tSU.STA
tHD.STA
tSU.STO
Start condition
Stop condition
SCL
SDA
Figure 32
Start/Stop Conditions
3.
Data transfer and acknowledgment signal
Data transmission is performed for every 1-byte, after detecting a start condition. Transmit data while the SCL line is in
“L”, and be careful of spec of tSU.DAT and tHD. DAT when changing the SDA line. If the SDA line changes while the SCL
line is in “H”, the data will be recognized as start/stop condition in spite of data transmission. Note that by this case, the
access will be interrupted.
During data transmission, every moment receiving 1-byte data, the devices which work for receiving data send an
acknowledgment signal back. For example, as seen in Figure 33, in case that the S-35390A is the device working for
receiving data and the master device is the one working for sending data; when the 8th clock pulse falls, the master
device releases the SDA line. After that, the S-35390A sends an acknowledgment signal back, and set the SDA line to
“L” at the 9th clock pulse. The S-35390A does not output an acknowledgment signal is that the access is not being
done regularly.
1
8
9
Output acknowledgment
(“L” active)
tPD
Start condition
SCL
(Input from
S-35390A)
SDA
(Output from
master device)
SDA
(Input from
S-35390A)
SDA is released
tSU.DAT
tHD.DAT
High-Z
Figure 33
Output Timing of Acknowledgment Signal
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