參數(shù)資料
型號: S-3530A
廠商: Seiko Instruments Inc.
英文描述: CMOS Real-Time Clock IC Supporting an IIC-Bus(支持IIC-BUS的CMOS實時時鐘芯片)
中文描述: CMOS實時時鐘IC支持一個IIC總線(支持IIC總線的實時時鐘芯片的CMOS)
文件頁數(shù): 5/31頁
文件大?。?/td> 201K
代理商: S-3530A
Real-Time Clock
S-3530A
4
Seiko Instruments Inc.
1-4.Acknowledge
Data transfer is performed in eight-bit sequence. A device on the system bus, which succeedingly receives data during a
period of a ninth clock cycle, puts the SDA line on "L" and returns an acknowledge signal meaning that the data has been
received.
1-5.Device addressing
The master device on the system generates a start condition to its slave device to make communication. It continuously
issues the device address of a four-bit length, the command of a three-bit length and the read/write command of a one-bit
length over the SDA bus.
The upper four bits, called a device code, represent a device address and are fixed at "0110".
Figure 5 Acknowledge output timing
Acknowledge
output
1
8
9
t
PD
t
DH
Start condition
SCL
(S-3530A input)
SDA
(Master output)
SDA
(S-3530A output)
Figure 6 Communication data
Command
0
1
1
0
C2
C1
C0
R/W
Device code
MSB
LSB
Read/Write bit
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