參數(shù)資料
型號(hào): S-3511AEFS-TB
元件分類: XO, clock
英文描述: REAL TIME CLOCK, PDSO8
封裝: 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù): 14/36頁(yè)
文件大?。?/td> 404K
代理商: S-3511AEFS-TB
REAL-TIME CLOCK
Rev. 1.4_00
S-3511A
Seiko Instruments Inc.
21
6. Power voltage detecting circuit
S-3511A has an internal power voltage detecting circuit. This circuit gives sampling movement for only
15.6 ms once a second. If the power voltage decreases below the detection voltage (VDET), the BLD latch
circuit latches the “H” level, and sampling movement stops. Only when subsequent communication is of
the status read command, the output of the latch circuit is transferred to the sift register and the sampling
movement is resumed. Decrease in power voltage can be monitored by reading the POWER flag. That is
to say, once decrease in power voltage is detected, any detecting operation is not performed and "H" is
held unless you perform initialization or send the status read command.
Caution When power voltage is increased and the first read operation is performed after decrease
in power voltage occurs and the latch circuit latches "H", "1" can be read on the POWER
flag. However, if the next read operation is performed after the sampling of the detecting
circuit, the POWER flag is reset since sampling is subsequently allowed. See the timing
diagram below.
Latch circuit output
Sampling pulse
(0)
1 s
Stop
(1)
(1) (1)
(1)
(0)
VDD
POWER flag
VDET
Communication
Latch circuit
output
Sampling pulse
Carry pulse
1 s
(1)
(0)
Communication
POWER flag
[Timing of sampling pulse]
0.5 s
7.8 ms
Carry-up timing
15.6 ms
Latch timing
1 Hz
VDET
Sampling pulse
(1)
(0)
VDD
Stop
Figure 17 Timing of the power voltage detecting circuit
DISCONTINUED
PRODUCT
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