參數(shù)資料
型號: S-3510AEFJA
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO8
文件頁數(shù): 5/20頁
文件大小: 153K
代理商: S-3510AEFJA
REAL-TIME CLOCK
S-3510 Series
12
Seiko Instruments Inc.
(6) Voltage Detector
The S-3510 series incorporates a voltage detector that performs sampling once a second for 62.5 msec.
When the supply voltage goes below the detection voltage, the BLD latch-up circuit latches “H,” and stops sampling.
[IMPORTANT]
The BLD flag can read 1 when the supply voltage increases and the first read is executed. After that, however, sampling is
permitted. Therefore, when the next read is performed after sampling of the detector, the BLD flag is reset. Refer to the
timing charts shown below:
When the CS is turned to “H,” the output of the latch-up circuit is transmitted to the shift register only when the subsequent
command is the READ command.
Reading the BLD bit allows the decrease in the voltage to be monitored.
If the CS is turned to “L” after completing the read, sampling restarts. That is, once a decrease in the voltage is detected,
detection is not performed and the status is kept “H” as long as an initialization is not performed or a READ command is not
sent.
Sampling
pulse
Carry pulse
(0)
1 sec
Halt
(1)
(1) (1)
(0)
VCC
CS
Latch circuit output
BLD flag
[Timing of Sampling Pulse]
1Hz
VDET
Sampling
pulse
0.5 sec
7.8 msec
Carry-up timing
Latch timing
62.5 msec
31.25 msec
62.5 msec
Latch pulse
Figure 11
Figure 12
Halt
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