
CMOS SERIAL E
2
PROM
S-29590A / 29690A
6
Operation
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK
when CS goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses
after CS goes high. Instruction input finishes when CS goes low, where it must be low between commands during t
CDS
.
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode. The start bit + instruction,
adress and data are 8-bit instructions. This makes it easy to prerare your own software using a serial interface
incorporated into the CPU.
1. Read
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, 16-bit data is
continuously output in synchronization with the falling of SK.
When all of the data (D15 to D0) in the specified address has been read, the data in the next address can be read with
the input of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous input of
SK clocks as long as CS is high.
The last address (An
A1 A0 = 1
11) rolls over to the top address (An
A1 A0 = 0
00).
Z
15
A0
A6
17
50
34
19
D15
D15 D14
D14D13
D14
Hi
-
Z
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+1
D13
D0
D1
D2
D15
Hi-Z
A1
A2
A3
A4
A5
A7
0
1
33
32
31
30
29
16
9
3
2
1
49
48
47
46
45
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+2
D13
D0
D1
D2
18
CS
SK
DI
DO
8
7
6
5
4
12
14
11
10
13
A9 A8
A10
0
0
*On the S-29590A, A
10
is optional.
Figure 4
Read Timing (S-29690A)