參數資料
型號: S-1312B23-M5T1U3
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: FIXED POSITIVE LDO REGULATOR, PDSO5
封裝: HALOGEN FREE AND LEAD FREE, SOT-23, 5 PIN
文件頁數: 10/41頁
文件大小: 523K
代理商: S-1312B23-M5T1U3
LOW CURRENT CONSUMPTION HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1312 Series
Rev.1.1_00
Seiko Instruments Inc.
18
Operation
1. Basic operation
Figure 16 shows the block diagram of S-1312 Series.
The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage
resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the constant
output voltage which is not influenced by the input voltage and temperature change, to the output transistor.
*1
*1. Parasitic diode
VSS
Current
supply
+
Vfb
Vref
VIN
VOUT
Rf
Rs
Error
amplifier
Reference voltage
circuit
Figure 16
2. Output transistor
In the S-1312 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that VOUT does not exceed VIN
+ 0.3 V to prevent the voltage regulator from being damaged due to inverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin.
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