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參數(shù)資料
| 型號： | S-1172B21-E6T1U |
| 元件分類： | 固定正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 2.1 V FIXED POSITIVE LDO REGULATOR, 0.15 V DROPOUT, PDSO6 |
| 封裝： | HALOGEN FREE AND LEAD FREE, HSOP-6 |
| 文件頁數(shù)： | 1/34頁 |
| 文件大?。?/td> | 478K |
| 代理商： | S-1172B21-E6T1U |
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ProASIC3 DC and Switching Characteristics
v1.3
2 - 83
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-106 ProASIC3 CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Serial Clock (SCLK) for Dynamic PLL1
125
MHz
Delay Increments in Programmable Delay Blocks2, 3
200
ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
(A3P250 and A3P1000 only)
LockControl = 0
300
s
LockControl = 1
300
s
(all other dies)
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 5
(A3P250 and A3P1000 only)
LockControl = 0
1.6
ns
LockControl = 1
1.6
ns
(all other dies)
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 12, 3
0.6
5.56
ns
Delay Range in Block: Programmable Delay 22, 3
0.025
5.56
ns
Delay Range in Block: Fixed Delay2, 3
2.2
ns
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. The A3P030 device does not contain a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-1172B21-U5T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B22-E6T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B22-U5T1G | 制造商:Seiko Instruments Inc (SII) 功能描述:LINEAR LDO REG HI 70UA IQ 1000MA IOUT |
| S-1172B23-E6T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
| S-1172B23-U5T1G | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR |
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