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參數(shù)資料
| 型號： | RTL8305S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-PORT 10/100 MBPS SINGLE CHIP SWITCH CONTROLLER |
| 中文描述： | 5端口10/100 Mbps單片開關(guān)控制器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 417K |
| 代理商： | RTL8305S |
RTL8305S
2002/02/19
Rev. 1.2
14
The other active-low input pin is P4FLCTRL#, which determines if flow control algorithm is enabled through the MII port.
(default P4FLCTRL#=1 )
If P4FLCTRL#=0 and P4DPXSTA#=0, 802.3x flow control packets will flow through the MII port.
If P4FLCTRL#=0 and P4DPXSTA#=1, a back-pressure algorithm will be implemented through the MII port.
If P4FLCTRL#=1, no flow control algorithm is performed on the MII port.
All three input pins, P4DPXSTA#, P4SPDSTA#, and P4FLCTRL#, have no effect when P4LNKSTA#=1.
It is important to note that the MRXD[3:0] pins in MII/SNI PHY mode are MTXD[3:0] for MII MAC mode, and vice versa.
Also the same for pin MRXDV vs. MTXEN, and pin MRXC vs. MTXC.
NOTE:
There are no MRXER, MTXER, MCRS and SMI (MDC/MDIO) pins for MII signaling. Because of the absence of
MCRS, system designers can wire MRXDV directly to CRS and RXDV of the opposite chip.
4
4
RTL8305S
60 MRXDV/MTXEN
67~61 MRXD[3:0]/MTXD[3:0]
51 MTXC/MRXC
52 MTXEN/MRXDV
57-54 MTXD[3:0]/MRXD[3:0]
58 COL
P4Mode[0]
P4Mode[1]
P4FlCtrl#
EnP4Led
P4LnkSta#
P4SpdSta#
P4DupSta#
SelMiiMac#
Not Used
59 MRXC/MTXC
Floating=High
x
x
Floating=High
x
x
x
Floating=High
Floating=High
Floating=High
Floating=High
x
x
Floating=High
x
All should be floating
5 UTP Mode (Default five port switch application)
For general cases, most of the option pins should be floating (=High=Enable), except EnBrdCtrl. This means that EnBrdCtrl
should be pulled down (=Low=Disable) for normal applications.
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