參數(shù)資料
型號(hào)： RT9205PS
廠商： Richtek Technology Corporation
英文描述： Dual Regulators - Synchronous Buck PWM DC-DC and Linear Controller
中文描述： 雙穩(wěn)壓器-同步降壓PWM型DC - DC和線性控制器
文件頁(yè)數(shù)： 12/15頁(yè)
文件大小： 227K
代理商： RT9205PS
RT9205/A
Preliminary
12
DS9205/A-08 March 2007
www.richtek.com
Input / Output Capacitor
High frequency/long life decoupling capacitors should be
placed as close to the power pins of the load as physically
possible. Be careful not to add inductance to the PCB
trace, as it could eliminate the performance from utilizing
these low inductance components. Consult with the
manufacturer of the load on specific decoupling
requirements.
The output capacitors are necessary for filtering output
and stabilizing the close loop (see the PWM loop stability).
For powering advanced high-speed processors, it is
required to meet fast load transient requirement. Also high
ESR usually induces ripple that may trigger UV or OV
protections. So High frequency capacitors with low ESR/
ESL capacitors are recommended here.
Linear Regulator Driver
The linear controller of RT9205/A was designed to drive an
external bipolar NPN transistor or a N-MOSFET. For a N-
Channel MOSFET, normally DRV need to provide minimum
V
OUT2
+VT+gate-drive voltage to keep V
OUT2
as the set
voltage. When driving MOSFET operating at a 5V power
supply, the gate-drive will be limited at 5V. At this situation,
as shown in Figure 7 a MOSFET with low VT threshold
(VT = 1V) and set Vout2 below 2.5V are suggested. In
V
BOOT
= 12V operation condition, as Figure 8 shown, VCC
is regulated higher than 6V, which providing higher gate-
drive capability for driving the MOSFET, V
OUT2
can be set
as V
OUT2
≤
3.3V.
PWM Loop Stability
The RT9205/A is a voltage mode buck controller designed
for 5V step-down applications. The gain of error amplifier
is fixed at 35dB for simplifying design.
The output amplitude of ramp oscillator is 1.6V, the loop
gain and loop pole/zero are calculated as follows :
The RT9205/A Bode plot is as shown in Figure 9. It is
stable in most of application conditions.
Figure 7
Figure 8
Figure 9
p
p
×
×
A
OUT
V
O
O
5
0.8
DC loop gain G = 35 dB
1.75
1
LC filter pole P =
2
LC
Error Amp pole P =300kHz
1
ESR zero Z =
2 ESR C
Loop Gain
40
30
20
10
1M
10k
1k
100
100k
V
OUT
= 3.3V
C
OUT
= 1500uF(33m
)
L = 2uH
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
P
O
= 2.9kHz
Z
O
= 3.2kHz
BOOT
VCC
DRV
FBL
RT9205/A
VCC = 5V
R4
R3
Max. 5V
Suggest Low
V
T
MOSFET
+
R4<1K
V
OUT2
< 2.5V
BOOT
VCC
DRV
FBL
RT9205/A
6V
R4
R3
Max. 6V
Suggest Low
V
T
MOSFET
V
OUT2
< 3.3V
+
R4<1K
V
BOOT
= 12V
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