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參數(shù)資料
| 型號(hào)： | RT9173GS |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Peak 3A Bus Termination Regulator |
| 中文描述： | 山頂3A條總線終端穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大小： | 317K |
| 代理商： | RT9173GS |
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RT9173/A
8
DS9173/A-18 March 2007
www.richtek.com
Application Information
Internal Parasitic Diode
Avoid forward-bias internal parasitic diode, V
OUT
to V
CNT
L
,
and V
OUT
to V
IN
, the V
OUT
should not be forced some
voltage respect to ground on this pin while the V
CNTL
or
V
IN
is disappeared.
Consideration while Designs the Resistance of
Voltage Divider
Make sure the sinking current capability of pull-down NMOS
if the lower resistance was chosen so that the voltage on
V
REFEN
is below 0.2V.
In addition, the capacitor and voltage divider form the low-
pass filter. There are two reasons doing this design; one is
for output voltage soft-start while another is for noise
immunity.
How to reduce power dissipation on Notebook PC or
the dual channel DDR SDRAM application
In notebook application, using RichTek's Patent
"
Distributed Bus Terminator Topology
"
with choosing
RichTek's product is encouraged.
R0
R9
R8
R7
R6
R5
R4
R3
R2
R1
RN
RN+1
RT9173/A
RT9173/A
VOUT
VOUT
REFEN
BUS(0)
BUS(1)
BUS(2)
BUS(3)
BUS(4)
BUS(5)
BUS(6)
BUS(7)
BUS(8)
BUS(9)
BUS(N)
BUS(N+1)
Terminator Resistor
Distributed Bus Terminating Topology
Figure 6
Thermal Consideration
RT9173/A regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed absolute maximum
operation junction temperature 125
°
C. The power
dissipation definition in device is :
P
D
= (V
IN
- V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
-T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125
°
C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance. The
junction to ambient thermal resistance
θ
JA
highly depends
on IC package, PCB layout, and the rate of surroundings
airflow.
θ
JA
for SOP-8 package is 160
°
C/W and TO-263-5
package is 52
°
C/W on standard JEDEC 51-3 (
single layer,
1S
) thermal test board. The maximum power dissipation
at T
A
= 25
°
C can be calculated by following
formula :
P
D(MAX)
= (125
°
C - 25
°
C) / (160
°
C/W)= 0.625W (SOP-8
package)
P
D(MAX)
= (125
°
C- 25
°
C) / (52
°
C/W)= 1.923W (TO- 263-
5 package )
Since the multiple V
CTRL
pins of the SOP-8 package are
internally fused and connected to lead frame, it is efficient
to dissipate the heat by adding cooper area on V
CTRL
footprint. Figure 7 shows the package sectional drawing
of SOP-8. Every package has several thermal dissipation
paths, as show in Figure 8, the thermal resistance
equivalent circuit of SOP-8. The path 2 is the main path of
thermal flow due to these materials thermal conductivity.
We define the center of multiple V
CTRL
pins are the case
point of the path 2.
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