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參數(shù)資料
| 型號： | RT9173D |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator |
| 中文描述： | 成本效益，峰值3A條接收器/源總線終端穩(wěn)壓器 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 233K |
| 代理商： | RT9173D |
RT9173D
11
www.richtek.com
DS9173D-05 September 2007
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9173D. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between RT9173D and the
preceding power converter.
Thermal Consideration
RT9173D regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed maximum operation
junction temperature 125
°
C. The power dissipation
definition in device is:
P
D
= (V
IN
- V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:
P
D(MAX)
= ( T
J(MAX)
-T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125
°
C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance. The
junction to ambient thermal resistance (
θ
JA
is layout
dependent) for SOP-8 package (Exposed Pad) is 75
°
C/W
on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at T
A
= 25
°
C can
be calculated by following formula:
P
D(MAX)
= (125
°
C - 25
°
C) / 75
°
C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 7, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Ambient
Molding Compound
Gold Line
Lead Frame
Die Pad
Case (Exposed Pad)
Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing
Figure 7. Thermal Resistance Equivalent Circuit
The thermal resistance
θ
JA
of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the expose pad of SOP-8 package.
About PCB layout
,
the Figure 8 show the relation between
thermal resistance
θ
JA
and copper area on a standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
T
A
= 25
°
C.We have to consider the copper couldn't stretch
infinitely and avoid the tin overflow. We use the
“
dog-bone
”
copper patterns on the top layer as Figure 9.
As shown in Figure 10, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad of 2 oz. copper (Figure 10.a),
θ
JA
is
75
°
C/W. Adding copper area of pad under the SOP-8
(Exposed Pad) (Figure 10.b) reduces the
θ
JA
to 64
°
C/W.
Even further, increasing the copper area of pad to 70mm
2
(Figure 10.e) reduces the
θ
JA
to 49
°
C/W.
Junction
R
DIE
R
DIE-ATTACH
R
DIE-PAD
R
GOLD-LINE
R
LEAD FRAME
Case
(Exposed Pad)
R
PCB
R
PCB
Ambient
R
MOLDING-COMPOUND
path 1
path 2
path 3
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