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參數(shù)資料
| 型號(hào)： | RT9014-PPPQW |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Ultra Low Noise 300mA Dual LDO Regulator with POR, NMOS Driver and Requiring No Bypass Capacitor |
| 中文描述： | 超低噪聲300mA的雙路LDO穩(wěn)壓器與葡萄牙，NMOS管驅(qū)動(dòng)器，無需旁路電容 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 400K |
| 代理商： | RT9014-PPPQW |
RT9014/A
Preliminary
2
DS9014/A-08 August 2007
www.richtek.com
Functional Pin Description
Pin No.
RT9014
-□□
PQW
RT9014A
-□□
Pin
Name
Pin Function
1
1
VIN
Supply Input.
2
--
EN
Chip Enable (Active High).
--
2
EN1
Chip Enable 1 (Active High).
--
3
EN2
Chip Enable 2 (Active High).
3
--
NC
No Internal Connection Pin.
4
4
SW
Active high signal drives open-drain N-MOSFET.
Note that this pin is high impedance. There should be a pull low
100
k
Ω
resistor connected to GND when the control signal is
floating.
5
5
SET
Delay Set Input: Connect external capacitor to GND to set the
internal delay for the POR output. When left open, there is no
delay. This pin cannot be grounded.
6
6
GND
Common Ground.
7
7
DRV
Open-Drain Output: Capable of sinking 150mA.
8
8
POR
Power-On Reset Output: Open-drain output. Active low indicates
an output under-voltage condition on regulator 2.
9
9
VOUT2 Channel 2 Output Voltage
10
10
VOUT1 Channel 1 Output Voltage
Exposed Pad (11) Exposed Pad (11) GND
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Typical Application Circuit
EN
SW
VOUT2
VOUT1
RT9014
GND
VIN
1uF
V
OUT1
1uF
V
OUT2
1uF
V
IN
POR
DRV
SET
Chip Enable
DRV Enable
C
DELAY
100K
100k
C
IN
C
OUT1
C
OUT2
EN1
SW
VOUT2
VOUT1
RT9014A
GND
VIN
1uF
V
OUT1
1uF
V
OUT2
1uF
V
IN
POR
DRV
SET
Chip Enable
DRV Enable
C
DELAY
100K
100k
C
IN
C
OUT1
C
OUT2
EN2
Marking Information
For marking information, contact our sales representative directly or through a Richtek distributor located in your area,
otherwise visit our website for detail.
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