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參數(shù)資料
| 型號： | RT9006BPSP |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Dual LDO Regulator with Reset Function |
| 中文描述： | 雙路LDO穩(wěn)壓器具有復位功能 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 211K |
| 代理商： | RT9006BPSP |
RT9006A/B
8
DS9006A/B-05 September 2007
www.richtek.com
Application Information
Detector Delay Time
The delay time (T
d
) of Reset signal from V
OUT2
can be
calculated from the formula :
IN2
I
V
IN2
is the input voltage of channel 2 and the I
CT
(2.6uA.Typ.)
is the CT pin sourcing current. C
CT
is the capacitance of
the external capacitor from CT pin to GND.
Current limit
The RT9006 contains two independent current limiters,
which monitors and controls the pass transistor
’
s gate
voltage, limiting the output current to a certain level. The
typical current limit level of channel 1 and channel 2 is
450mA and 600mA respectively.
Thermal Consideration
For continued operation, do not exceed absolute maximum
operation junction temperature 125
°
C. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, the rate of surroundings airflow and
temperature difference between junction to ambient. The
maximum power dissipation can be calculated by following
formula :
P
D(MAX)
= ( T
J(MAX)
T
A
) /
θ
JA
Where
T
J(MAX)
: The maximum operation junction temperature
125
°
C.
T
A
: The operated ambient temperature.
θ
JA
: The junction to ambient thermal resistance.
The junction to ambient thermal resistance for SOP-8
(Exposed Pad) package is 75
°
C/W on the standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board. The
copper thickness is 2oz. The maximum power dissipation
at T
A
= 25
°
C can be calculated by following formula :
P
D(MAX)
= (125
°
C
25
°
C) / 75
°
C/W = 1.33W {SOP-8
(Exposed Pad) packages}
Figure 1. Derating Curves for
SOP-8 (Exposed Pad)
Package
PCB Layout Considerations
The thermal resistance
θ
JA
of
SOP-8 (Exposed Pad)
is
determined by the package design and the PCB design.
However, the package design had been designed. If
possible, it's useful to increase thermal performance by
the PCB design. The thermal resistance
θ
JA
can be
decreased by adding a copper under the exposed pad of
SOP-8 (Exposed Pad)
package.
As shown in Figure 2, the amount of copper area to which
the
SOP-8 (Exposed Pad)
is mounted affects thermal
performance. When mounted to the standard
SOP-8
(Exposed Pad)
pad (Figure 2.a),
θ
JA
is 75
°
C/W. Adding
copper area of pad under the
SOP-8 (Exposed Pad)
(Figure 2.b) reduces the
θ
JA
to 64
°
C/W. Even further,
increasing the copper area of pad to 70mm
2
(Figure 2.e)
reduces the
θ
JA
to 49
°
C/W.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0
16.25 32.5 48.75
65
81.25 97.5 113.8
130
Ambient Temperature
P
(
°
C)
Copper Area
70mm
2
50mm
2
30mm
2
10mm
2
Min. layout
4-Layers PCB
CT
x V
0.8
x
C
T
CT
d
=
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal resistance
θ
JA
. For SOP-8 (Exposed Pad) packages, the Figure 1 of
de-rating curves allows the designer to see the effect of
rising ambient temperature on the maximum power allowed.
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