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參數(shù)資料
| 型號(hào)： | RT8805C |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Two Phase General Purpose PWM Controller |
| 中文描述： | 兩相通用PWM控制器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 391K |
| 代理商： | RT8805C |
RT8805C
Preliminary
11
DS8805C-03 August 2007
www.richtek.com
Figure 3. Current Sensing Loop
The sensing circuit gets I
X
= I
L(S/H)
x R
DS(ON)
x GM by
local feedback. I
X
is sampled and held just before low side
MOSFET turns off (See Figure 4). Therefore,
I
X(S/H)
= I
L(S/H)
x R
DS(ON)
x GM
Figure 4. Inductor Current and Gate signals
GM
R
2L
s
5
V
V
IN
V
V
I
I
200kHz
F
s,
5
V
V
IN
V
T
,
2
T
L
V
I
I
DS(ON)
OUT
IN
OUT
L(AVG)
(S/H)
X
SW
OUT
IN
OFF
OFF
OUT
L(AVG)
L(S/H)
×
×
×
×
=
=
×
=
×
=
μ
μ
High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Inductor Current
Falling Slope = V
OUT
/L
I
L
I
L(AVG)
I
L(S/H)
Gate control
a. Before SS signal reach the valley of the ramp voltage,
UGATE and LGATE will be off.
b. If SS pin is pulled down 0.4V, UGATE and LGATE will
be off.
c. UV protect function caused by FB < 0.6V and SS >
3.7V, and controller will trigger Always Hiccup Mode.
d. When OC function occurs and SS > 3.7V, a constant
current of 10
μ
A starts to discharge the capacitor
connected to SS pin right away. When OC occurs,
UGATE and LGATE will be off. When the voltage at the
capacitor connected to SS pin pass about 0.4V, a
constant current of 10
μ
A starts to charge the capacitor.
The PWM signal is enable to pass to UGATE and
Current Balance
RT8805C senses the voltage drop of the low-side MOS
and translates this to control the ramp signal. We can see
that the voltage signal finally injected to channel one is
proportional to (I
L1
- I
L2
). Channel two is proportional to
(I
L2
- I
L1
). In steady state and current balance situation,
there is no sensed signal injected into the ramp.
If I
L1
> I
L2
, the ramp bottom of channel 1 will be lifted up
and decreased the duty of UGATE1. On the other hand,
the ramp bottom of channel 2 will be pulled low to increase
the duty of UGATE2. Finally, the loop will be back to the
balance state through above mentioned negative feedback
scheme. Figure 5 shows this scheme.
Figure 5. Current Balance
Logic
&
Driver
L2
I
L2
+
-
k2 = k x R
ON2
V
ON2
V
IN2
Logic
&
Driver
L1
I
L1
+
-
k1 = k x R
ON1
V
ON1
V
IN1
CL
RL
V
OUT
V
CSO2
= k2 x I
L2
= k x V
ON2
V
CSO1
= k1 x I
L1
= k x V
ON1
2
1
RAMP2
RAMP1
+
-
V
REF
COMP
RAMP2
RAMP1
Current
Balance
OCP
S/H
+
-
MUX
PHASE1
PHASE2
CLK2
CLK1
OC
IMAX
GM
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