參數(shù)資料
型號: RT8803A
廠商: Richtek Technology Corporation
英文描述: 2/3-Phase PWM Controller for High-Density Power Supply
中文描述: 2/3-Phase PWM控制器的高密度電源
文件頁數(shù): 22/27頁
文件大?。?/td> 553K
代理商: RT8803A
RT8803A
22
DS8803A-05 August 2007
www.richtek.com
All brandname or trademark belong to their owner respectively
Consequently, the sensing current I
X
is proportional to
inductor current I
LX
and is expressed as :
DCRx
I
I
=
The sensed current I
X
is used for current balance and droop
tuning as described as followe
d. Since all phases share
one common GM, GM offset and linearity variation effect
is eliminated in practical applications. As sub-milli-ohm-
grade inductors are widely used in modern mother boards,
slight mismatch of GM amplifiers offset and linearity results
in considerable current shift between phases. The time-
sharing DCR current sensing technical is extremely
important to guarantee phase current balance in mass
production.
Phase Current Balance
The sampled and held phase current I
X
are summed and
averaged to get the averaged current . Each phase
current I
X
then is compared with the averaged current.
The difference between I
X
and is injected to
corresponding PWM comparator. If phase current I
X
is
smaller than the averaged current , RT8803A increases
the duty cycle of corresponding phase to increase the
phase current accordingly and vice versa.
X
X
Figure 2. Vcore Response at VID on the Fly
V
CORE
VID7
PWM3
DCR Current Sensing
RT8803A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 3. Current sensing amplifier
GM samples and holds voltages VCx across the current
sensing capacitor Cx by turns in a switching cycle.
According to the Basic Circuit Theory, if
Figure 3
DCRx
I
VCx
then
Cx
Rx
DCRx
Lx
LX
×
=
×
=
CSNX
LX
X
R
×
CSA
R
CSN1
R
CSN3
R
CSN2
T1
T3
T2
T1
T3
T2
CSA: Current Sense Amplifier
I
X
I
X
= I
LX
x DCR
X
/R
CSNX
T1
T2
T3
ISP1
ISN1
ISP3
ISN23
ISP2
ISN23
S/H CKT
+
-
L1
DCR1
L2
DCR2
L3
DCR3
R1
C1
+ VC1 -
R3
C3
+ VC3 -
R2
C2
+ VC2 -
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