參數(shù)資料
型號(hào): RT8100APQV
廠商: Richtek Technology Corporation
英文描述: Synchronous buck PWM DC/DC with Dual Voltage Control Mode
中文描述: 同步降壓PWM直流/雙直流電壓控制模式
文件頁數(shù): 15/18頁
文件大?。?/td> 434K
代理商: RT8100APQV
RT8100A
Preliminary
15
DS8100A-01 August 2007
www.richtek.com
CSN
L
X
R
I
DCR
I
×
=
The PWM signal is enable to pass to the UGATE and
LGATE. If the OC protection occurs three times, OCSD
will be activated and shut down the chip and pull low PI
about 15
μ
s in tracking mode.
RT8100A uses an external resistor R
CSN
to set a programm-
able over current trip point. OCP comparator compares
inductor current with this reference current. RT8100A uses
hiccup mode to eliminate fault detection of OCP or reduce
output current when output is shorted to ground.
Figure 12
+
-
I
X
80
μ
A
OCP comparator
OTP
Monitor the temperature near the driver part within the chip.
Shutdown the chip when OTP.
Component Selection
Components should be appropriately selected to ensure
stable operation, fast transient response, high efficiency,
minimum BOM cost and maximum reliability.
Output Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. For a synchronous buck converter, the ripple
current of inductor (
Δ
I
L
) can be calculated as follows :
Generally, an inductor that limits the ripple current between
20% and 50% of output current is appropriate. Make sure
that the output inductor could handle the maximum output
current and would not saturate over the operation
temperature range.
Output Capacitor Selection
The output capacitors determine the output ripple voltage
(
Δ
V
OUT
) and the initial voltage drop after a high slew-rate
load transient. The selection of output capacitor depends
on the output ripple requirement. The output ripple voltage
is described as follows :
D)
(1
C
x
L
x
f
V
x
8
1
ESR
x
Δ
I
Δ
V
OUT
2
OSC
OUT
L
OUT
+
=
L
x
f
x
V
V
x
)
V
(V
Δ
I
OSC
IN
OUT
OUT
IN
L
=
For electrolytic capacitor application, typically 90~95% of
the output voltage ripple is contributed by the ESR of output
capacitors. Paralleling lower ESR ceramic capacitor with
the bulk capacitors could dramatically reduce the equivalent
ESR and consequently the ripple voltage.
Input Capacitor Selection
Use mixed types of input bypass capacitors to control the
input voltage ripple and switching voltage spike across the
MOSFETs. The buck converter draws pulsewise current
from the input capacitor during the on time of upper
MOSFET. The RMS value of ripple current flowing through
the input capacitor is described as :
The input bulk capacitor must be cable of handling this
ripple current. Sometime, for higher efficiency the low ESR
capacitor is necessarily. Appropriate high frequency
ceramic capacitors physically near the MOSFETs effectively
reduce the switching voltage spikes.
MOSFET Selection
The selection of MOSFETs is based upon the
considerations of R
DS(ON)
, gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as :
P
P
P
+
=
where T
RISE
and T
FALL
are rising and falling time of V
DS
of
upper MOSFET respectively. R
DS(ON)
and Q
G
should be
simultaneously considered to minimize power loss of upper
MOSFET.
The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is express as :
D)
(1
x
D
x
I
I
OUT
IN(RMS)
=
OSC
FALL
T
RISE
(T
IN
OUT
I
DS(ON)
OUT
I
SW_UPPER
_UPPER
COND
UPPER
f
x
)
x
x V
2
1
D
x
R
x
+
+
=
OSC
DIODE
T
x
F
OUT
I
OSC
IN
RR
DS(ON)
OUT
1
DIODE
x V
RR
Q
_LOWER
(1
x
COND
P
LOWER
I
=
f
x
x V
x
2
f
x
D)
R
x
P
P
P
+
+
+
+
=
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