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參數(shù)資料
| 型號： | RT8100A |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Synchronous buck PWM DC/DC with Dual Voltage Control Mode |
| 中文描述： | 同步降壓PWM直流/雙直流電壓控制模式 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 434K |
| 代理商： | RT8100A |
RT8100A
Preliminary
6
DS8100A-01 August 2007
www.richtek.com
Power on reset
The POR circuitry monitors the supply voltage of the chip.
When the chip power supply exceeds 4.2V, the chip
releases the reset state and works according to the
settings. Once the supply voltage is lower than 4.0V, POR
circuitry resets the chip.
V
IN
detection
The V
IN
detection circuitry monito
rs the switching power
source when power up. As V
IN
> 1.8V, RR pin is enabled
for ramp setting and the chip is in ramp setting mode. The
voltage at RR pin will be about 0.5V. Otherwise, the chip
will be in V
IN
detection mode and RR pin is disabled for
ramp setting until V
IN
> 1.8V. In V
IN
detection mode, the
UGATE and LGATE will be off and SS will be pulled low by
a constant current of 10uA. The chip will enter the ramp
setting mode and SS will re-softstart when V
IN
> 1.8V.
Enable
After POR reset, the chip monitors the voltage of PI pin.
When PI is higher than 0.3V, the chip is e
nabled. The chip
is disabled when V
PI
is lower than 0.3V. With a precise
threshold voltage, the PI pin can be used for power
sequence.
Soft-start
A constant current of 10uA starts to charge the capacitor
connected to SS pin right after the chi
p has been powered
up and enabled. The ramp voltage on SS pin is also used
to clamp the comp voltage during soft-start, which
automatically constraints the output current due to the
nature of current mode topology. This brings up sma
ller
inrush current and smooth output voltage ramp. The SS
pins are also used as the timer during OCP hiccup.
Frequency setting
The converter switching frequency is programmed by
connecting a resistor from the RT pin to GND. The
frequency vs. R
RT
plot is shown in
“
Typical Operating
Characteristics
”
.
Output voltage setting and control
Control loops consist of an error amplifier, a pulse width
modulator, current feed back components, a gate driver
and power components. The internal high accuracy bias
provides the reference voltage of 0.8V at the non-inverting
input of both error amplifiers. The output voltage is
programmed by using a voltage divider at output and feeding
the voltage division back to corresponding error amplifiers.
As conventional current mode PWM controller, the output
voltage is locked at the V
REF
of error amplifier and the error
signal is used as the control signal of pulse width
modulator. The PWM signals are generated by comparison
of EA output and current ramp waves. Power stage
transforms V
IN
to output by PWM signal on-time ratio.
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相關(guān)代理商/技術(shù)參數(shù) |
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