參數(shù)資料
型號(hào)： RT8100
廠商： Richtek Technology Corporation
英文描述： Synchronous buck PWM DC/DC with Dual Voltage Control Mode
中文描述： 同步降壓PWM直流/雙直流電壓控制模式
文件頁(yè)數(shù)： 13/18頁(yè)
文件大小： 438K
代理商： RT8100
RT8100
Preliminary
13
DS8100-03 August 2007
www.richtek.com
Feedback Loop Compensation
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the RR pin.
This keeps the modulator gain constant when the input
voltage varies. Second, the inductance valley current
proportional signal is derived from the voltage drop across
the ESR of the inductance is added to the ramp signal.
This effectively creates an internal current control loop.
The resistor connected to the CSN pin sets the gain in the
current feedback loop. The following expression estimates
the required value of the current sense resistor depending
on the maximum load current and the value of the
inductance DCR.
DCR
x
I
R
MAX
CSN
μ
A
80
=
1) Modulator Frequency Equations
RT8100 is a analogous current mode buck converter using
the high gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier), as Figure 6
shown.
The Transconductance :
Δ
I
GM
=
Δ
V
M
= (EA+) - (EA-) ;
Δ
I
OUT
= E/A output current.
M
OUT
Δ
V
Figure 6. OTA Topology
This transfer function of OTA is dominated by a higher DC
gain and the output filter (L
OUT
and C
OUT
) with a double
pole frequency at F
LC
and a zero at F
ESR
. The DC gain of
the modulator is the input voltage (V
IN
) divided by the peak
to peak oscillator voltage V
RAMP
.
V
OUT
R
OUT
GM
EA+
EA-
-
+
OUT
OUT
P(LC)
F
C
L
2
1
×
×
=
π
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
1
F
OUT
×
×
π
ESR
C
2
Z(ESR)
=
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
C
and Z
F
as Figure 7 shown.
Figure 7. Compensation Loop
+
×
×
×
=
×
×
=
×
×
=
C2
C1
C2
C1
R2
2
1
F
C1
R1
2
1
F
C2
R2
2
1
F
P2
P1
Z1
π
π
π
Figure 8 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fast transient response,
but often jeopardize the system stability. In order to cancel
one of the LC filter poles, place F
Z1
before the LC filter
resonant frequency. In the experience, place F
Z1
at 10%
LC filter resonant frequency. Crossover frequency should
be higher than the ESR zero but less than 1/5 of the
switching frequency. The F
P2
should be place at half the
switching frequency.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as follows :
+
-
GM
V
REF
V
COMP
C2
R2
C1
R
F
V
OUT
FB
R1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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RT8100GQV 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:Synchronous buck PWM DC/DC with Dual Voltage Control Mode
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