
RT8058
Preliminary
13
DS8058-02 August 2007
www.richtek.com
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is
“
chopped
”
between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (D) as follows :
R
SW
= R
DS(ON)TOP
x D + R
DS(ON)BOT
x (1
D)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current. Other losses including C
IN
and C
OUT
ESR
dissipative losses and inductor core losses generally
account for less than 2% of the total loss.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125
°
C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= ( T
J(MAX)
- T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125
°
C, T
A
is the ambient temperature and
the
θ
JA
is the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8058, where T
J(MAX)
is the maximum junction
temperature of the die and T
A
is the maximum ambient
temperature. The junction to ambient thermal resistance
θ
JA
is layout dependent. For WQFN-16L 3x3 packages,
the thermal resistance
θ
JA
is 68
°
C/W on the standard
JEDEC 51-7 four-layers thermal test board.
The maximum power dissipation at T
A
= 25
°
C can be
calculated by following formula :
P
D(MAX)
= ( 125
°
C
25
°
C ) / 68
°
C/W = 1.471 W for
WQFN-16L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance
θ
JA
. For RT8058 packages, the Figure 2 of
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8058.
}
A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
}
Connect the terminal of the input capacitor(s), C
IN
, as
close as possible to the PVDD pin. This capacitor provides
the AC current into the internal power MOSFETs.
}
LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise pick-
up.
}
Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVDD, VDD, VOUT, PGND, GND, or any other
DC rail in your system).
}
Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and GND.
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
Figure 2. Derating Curves for RT8058 Package
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
25
50
75
100
125
150
Ambient Temperature (
°
C)
M
Four Layers PCB