參數(shù)資料
型號(hào): RS5C316B
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: 0.65 MM PITCH, SSOP-8
文件頁數(shù): 29/38頁
文件大?。?/td> 288K
代理商: RS5C316B
RS5C316A/B
25
Interrupt cycle register
INTR output
Description
CT
3
CT
2
*
*
1
*
*
*
0
CT
1
CT
0
0
0
0
OFF
Interrupt halt
0
0
1
ON
Fixing the INTR pin to the low level
0
1
0
0.977ms
Cycle: 0.977ms (1/1024Hz) Duty 50%
0
1
1
0.5s
Cycle: 0.5s (1/2Hz)
1
0
0
1s
Every second
1
0
0
1
10s
Every 10 seconds
(For display of second digits: 00, 10, 20, 30, 40 and 50)
1
0
1
0
1 minute
Every minute (00 second)
1
0
1
1
10 minutes
Every 10 minutes
(For display of minute digits: 00, 10, 20, 30, 40 and 50)
1
1
0
0
1 hour
Every hour (00 minute and 00 second)
1
1
0
1
1 day
Every day (0 hour, 00 minute and 00 second a.m.)
1
1
1
0
1 week
Every week (0 week, 0 hour, 00 minute and 00 second a.m.)
1
1
1
1
1 month
Every month (1st day, 0 hour, 00 minute and 00 second a.m.)
10.2 Periodic (Clock) Interrupt
The INTR pin output, the interrupt cycle register, and the CTFG bit can be used to interrupt the CPU in a certain
cycle. The interrupt cycle register can be used to select either one of two interrupt output modes: the pulse mode
(when the CT
3
bit is set to 0) and the level mode (when the CT
3
bit is set to 1).
10.2-1 Interrupt Cycle Selection
10.2-2 Pulse mode Interrupt
When the CT
3
bit is set to 0 and provides four interrupt cycles, off, on, 1024Hz, and 2Hz can be selected. The
CTFG bit cannot be set because it is used for output monitoring.
10.2-3 Level mode Interrupt
When the CT
3
bit is set to 1, clock-interlocked cycles in increments of one second to one month can be selected.
The CTFG bit can be written; writing 1 to the CTFG bit switches the INTR pin to the low level while writing 0 to the
CTFG bit turns off the INTR pin.
*
1) The “
*
” mark indicates 0 or 1.
T1
0.488ms
CTFG
INTR
Interrupt
(Second count-up)
Interrupt
(Second count-up)
Writing 0 to CTFG bit
CTFG
INTR
1024Hz : T1= 0.977ms
2Hz
: T1= 500ms
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