
PRODUCT SPECIFICATION
RM3182A
3
Output Drive Capability and
Capacitive Loads
The Traditional Approach
The RM3182A is capable of driving a high capacitive/resis-
tive load. If complete ARINC compliance is required then
Out A and Out B pins are recommended to maintain the
output impedance. In this configuration, driving the full
ARINC load of 30nF || 400
W
the output characteristic takes
on the transfer function of a low pass filter due to the internal
37.5
W
resistor, the line resistance and the capacitance associ-
ated with the cable. This will result in a lower rise/fall time
of the device. Equation 1.1 relates the output voltage at Out
A and Out B to the voltage at the power amplifier’s output.
Output A is taken for this example:
1.1
Where: R
OUT
= 37.5
W
and Z
L
= R
L
|| C
L
The output as a function of frequency is given by equation
1.2.
1.2
Using equation 1.2, a time constant can be determined for
the given application which is shown in equation 1.3.
1.3
So, for the maximum loading condition of 30nF || 400
resulting time constant is 1.9
maximum load, the output waveform is greatly affected by
the low pass filter combinabon of the R
the load capacitance.
W
the
m
s. This shows that with a
OUT
|| R
L
resistor and
A New Option: Amp A/Amp B
The RM3182A also provides the user the option of connect-
ing the data line directly to the power output amplifiers thus
bypassing the internal 37.5
W
resistance of the device and
matching the line more precisely. For example, using a 1%
37.5
W
resistor allows better control of the output impedance.
By applying the load directly to the power amplifiers output
pins, the resulting waveform is virtually unchanged when
driving other loads. There may be applications where these
pins present a more desirable result. For instance, if the line
that the chip is driving is short, then the parasitic compo-
nents of the line can be neglected, and power amplifier can
be tied directly to the lines. This option can be utilized to
achieve a greater noise immunity through bypassing the
internal resistors.
Out A
AmpA Z
2
L
2
¤
)
¤
(
R
OUT
+
-Z
=
A
OUT
j
w
(
)
Amp A j
w
(
)
R
(
R
L
2R
OUT
1
j
w
C
L
R
L
+
)
+
------------------------------------------------------------------
=
t
R
OUT
R
L
||
(
)
C
L
=
Pin Assignments
V
REF
Rate Select
Sync
Data A
C
A
Out A
V
EE
GND
V
LOGIC
Amp B
Clock
Data B
C
B
Out B
Amp A
V
CC
65-4192
NC
65-4193
Data A
NC
NC
C
A
NC
NC
Clock
NC
Data B
C
B
NC
Amp A
NC
N
O
V
E
G
V
C
O
N
S
R
N
V
R
V
L
N
A