參數(shù)資料
型號(hào)： RIVA128
廠商： 意法半導(dǎo)體
英文描述： RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR
中文描述： 麗娃128⑩128位3D多媒體加速器
文件頁(yè)數(shù)： 8/85頁(yè)
文件大?。?/td> 609K
代理商： RIVA128
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
8/85
2.5
DEVICE ENABLE SIGNALS
2.6
DISPLAY INTERFACE
2.7
VIDEO DAC AND PLL ANALOG SIGNALS
2.8
POWER SUPPLY
Signal
I/O
Description
ROMCS#
O
Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used
in conjunction with framebuffer data lines as described abovein Section 2.3.
Signal
I/O
Description
SDA
I/O
Used for DDC2B+ monitor communication and interface to video decoder devices.
SCL
I/O
Used for DDC2B+ monitor communication and interface to video decoder devices.
VIDVSYNC
O
Vertical sync supplied to the display monitor.No bufferingis required. In TV mode this sig-
nal supplies composite sync to an external PAL/NTSCencoder.
VIDHSYNC
O
Horizontal sync supplied to the display monitor. No buffering is required.
Signal
I/O
Description
RED,
GREEN,
BLUE
COMP
O
RGB display monitor outputs. These are software configurableto drive either a doubly ter-
minated or singly terminated 75
load.
-
External compensation capacitor for the video DACs. This pin should be connected to
DACVDD
via the compensation capacitor, see Figure 66, page 60.
A precision resistor placed between this pin and GND sets the full-scale video DAC cur-
rent, see Figure 66, page 60.
A capacitor should be placed between this pin and GND as shown in Figure 66, page 60.
A series resonant crystal is connected between these two points to provide the reference
clock for the internal MCLK and VCLK clock synthesizers,see Figure 66 and Table20,
page 60. Alternately, an external LVTTLclock oscillator output may be driven into
XTA-
LOUT
, connecting
XTALIN
to GND. For designs supporting TV-out,
XTALOUT
should be
driven by a referenceclock as described in Section 11.6, page 61.
RSET
-
VREF
XTALIN
XTALOUT
-
I
O
Signal
I/O
Description
DACVDD
PLLVDD
VDD
GND
MPCLAMP
P
P
P
P
P
Analog power supply for the video DACs.
Analog power supply for all clock synthesizers.
Digital power supply.
Ground.
MPCLAMP
is connected to +5V to protect the 3.3V RIVA128ZXfrom external devices
which will potentially drive 5V signal levelsonto the Video Port input pins.
HOSTVDD
is connected to the Vddq 3.3 pins on the AGP connector. This is the supply
voltage for the I/O buffersand is isolated from the core VDD.On AGP designs these pins
are also connected to the
HOSTCLAMP
pins. On PCI designs they are connected to the
3.3V supply.
HOSTCLAMP
is the supply signalling rail protection for the host interface. In AGPdesigns
these signals are connected to Vddq 3.3. For PCI designs they are connected to the I/O
power pins (V
(I/O)
).
HOSTVDD
P
HOSTCLAMP
P
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